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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 18:13:40 +02:00
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fc462c8243d60ebd769d5ce01142fb7ed49fa8f8
yosys/frontends
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Clifford Wolf fc462c8243 Call "read_verilog" with -defer from "read"
Signed-off-by: Clifford Wolf <[email protected]>
2019-07-29 10:29:36 +02:00
..
aiger
Fix missing semicolon in Windows-specific code in aigerparse.cc.
2019-07-14 13:52:27 -04:00
ast
initialize noblackbox and nowb in AstModule::clone
2019-07-22 10:37:40 +02:00
blif
Add missing "[options]" to read_blif help
2019-02-08 12:41:39 -08:00
ilang
Allow attributes on individual switch cases in RTLIL.
2019-07-08 11:34:58 +00:00
json
Add upto and offset to JSON ports
2019-06-21 19:47:25 +02:00
liberty
Fix typo, double "of"
2019-07-16 11:03:30 +02:00
verific
Call "read_verilog" with -defer from "read"
2019-07-29 10:29:36 +02:00
verilog
Merge pull request #1147 from YosysHQ/clifford/fix1144
2019-07-03 12:30:37 +02:00
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