This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-09-06 20:12:09 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
fb83719745e67ae1bfcd6e977438cbd2bcedf248
yosys
/
techlibs
/
intel
T
History
nella
fff034d2f8
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00
..
common
Fixed data/address width parameters
2024-03-06 02:45:07 +01:00
cyclone10lp
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneive
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
max10
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
Makefile.inc
synth_intel: Remove incomplete Arria 10 GX support.
2020-08-21 01:46:06 +02:00
synth_intel.cc
Add check before flatten in synth_*.
2026-05-05 14:06:58 +02:00
