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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-05 19:36:55 +02:00
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fb83719745e67ae1bfcd6e977438cbd2bcedf248
yosys/passes
T
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Leo Moser fb83719745 memlib: fix documentation for PORT_<name>_CLK_POL
Signed-off-by: Leo Moser <[email protected]>
2026-05-09 10:28:07 +02:00
..
cmds
xprop: ignore $scopeinfo cells
2026-04-21 10:52:50 +02:00
equiv
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes
2026-03-04 14:47:57 +00:00
fsm
fsm_detect: add adff detection
2025-11-06 23:29:47 +02:00
hierarchy
hierarchy.cc: Tidying
2025-10-15 09:42:47 +13:00
memory
memlib: fix documentation for PORT_<name>_CLK_POL
2026-05-09 10:28:07 +02:00
opt
share: remove -force
2026-05-04 21:34:19 +02:00
pmgen
Fix typo in pmgen/README.md
2026-04-02 10:24:31 -05:00
proc
proc_clean: Removing an empty full_case is doing something
2026-01-07 13:10:32 +13:00
sat
Add comments to make sure it is clear scale is an exponent of 10
2026-04-23 17:22:14 +01:00
techmap
Merge pull request #5817 from YosysHQ/emil/clockgate-reject-sdffe
2026-05-08 18:38:51 +00:00
tests
test_cell.cc: Generate .aag for all compatible cells
2025-12-02 14:03:36 +13:00
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