Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
fb7af093a88daf9fa20fb7c45877686f5516808b
yosys/techlibs
T
History
Lofty fb7af093a8 intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
..
achronix
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
anlogic
…
common
Add bitwise $bweqx and $bwmux cells
2022-11-30 18:24:35 +01:00
coolrunner2
…
easic
…
ecp5
ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model
2023-04-06 10:18:48 +01:00
efinix
…
fabulous
fabulous: Add support for LUT6s
2023-04-12 18:42:09 +02:00
gatemate
gatemate: Enable register initialization
2023-02-15 17:29:01 +01:00
gowin
Merge pull request #3737 from yrabbit/all-primitives-script
2023-05-09 11:13:51 +02:00
greenpak4
…
ice40
ice40: Fix path delay definitions
2023-03-10 10:48:05 +01:00
intel
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
intel_alm
intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
machxo2
Add PLL and EBR related primitives
2023-04-10 12:39:09 +02:00
nexus
nexus: Fix BRAM write enable in PDP mode
2023-01-04 17:59:36 +01:00
quicklogic
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
sf2
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
xilinx
Update Xilinx cell definitions, fixes #3699
2023-03-23 09:44:36 +01:00
.gitignore
…
Powered by Gitea Version: 1.27.2 Page: 3388ms Template: 196ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API