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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 11:07:41 +02:00
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fb5b070e7e9e22b02a3ee94217c8ae20cef41f0b
yosys/techlibs/intel_alm
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Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes.
Fixes #2058.
2020-05-19 01:42:40 +02:00
..
common
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
Makefile.inc
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
synth_intel_alm.cc
synth_*: no need to explicitly read +/abc9_model.v
2020-05-14 10:33:56 -07:00
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