mirror of https://github.com/YosysHQ/yosys.git
30 lines
569 B
Systemverilog
30 lines
569 B
Systemverilog
module opt_compact_prefix_pack64 (
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input logic [63:0] sig,
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output logic [63:0] sig2
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);
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always_comb begin
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sig2 = '0;
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for (int I = 0, indx = 0; I < 64; I++) begin
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if (sig[I]) begin
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sig2[indx] = sig[I];
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indx += 1;
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end
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end
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end
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endmodule
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module opt_compact_prefix_pack128 (
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input logic [127:0] sig,
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output logic [127:0] sig2
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);
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always_comb begin
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sig2 = '0;
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for (int I = 0, indx = 0; I < 128; I++) begin
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if (sig[I]) begin
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sig2[indx] = sig[I];
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indx += 1;
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end
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end
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end
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endmodule
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