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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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fa5fc3f6afd9eb27c1f52244b60cbeb77aa2e26c
yosys/passes
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Clifford Wolf 3da5288ce0 Use input default values in hierarchy pass
Signed-off-by: Clifford Wolf <[email protected]>
2019-06-19 11:49:20 +02:00
..
cmds
Major rewrite of wire selection in setundef -init
2019-06-05 10:26:48 +02:00
equiv
Add -undef option to equiv_opt, passed to equiv_induct
2019-04-26 11:16:48 -07:00
fsm
fsm_opt: Fix runtime error for FSMs without a reset state
2019-02-07 10:35:36 +00:00
hierarchy
Use input default values in hierarchy pass
2019-06-19 11:49:20 +02:00
memory
memory_bram: Fix multiport make_transp
2019-04-07 16:56:31 +01:00
opt
Fix typo in opt_rmdff
2019-06-05 14:08:14 -07:00
pmgen
Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
2019-05-28 17:17:56 +02:00
proc
Improve proc full_case detection and handling, fixes #931
2019-04-18 15:13:47 +02:00
sat
Error out if no top module given before 'sim'
2019-06-05 14:16:24 -07:00
techmap
Allow muxcover costs to be changed
2019-06-07 08:34:11 -07:00
tests
flowmap: implement depth relaxation.
2019-01-08 01:13:05 +00:00
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