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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 11:29:42 +02:00
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f96d82a5f1982ea86cf02182b33abe91c015b10d
yosys/techlibs/xilinx
T
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Eddie Hung f96d82a5f1 Add -nocarry option to synth_xilinx
2019-04-24 16:46:41 -07:00
..
tests
Improved xilinx "bram1" test
2015-04-09 17:12:12 +02:00
.gitignore
…
abc.box
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 12:14:37 -07:00
abc.lut
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 12:14:37 -07:00
arith_map.v
Changes required for VPR place and route synth_xilinx.
2019-03-01 12:02:27 -08:00
brams_bb.v
…
brams_init.py
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
brams_map.v
Revert BRAM WRITE_MODE changes.
2019-03-04 09:22:22 -08:00
brams.txt
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
cells_map.v
Tweak
2019-04-22 17:59:56 -07:00
cells_sim.v
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 12:14:37 -07:00
cells_xtra.sh
Merge remote-tracking branch 'origin' into xc7srl
2019-04-20 10:41:43 -07:00
cells_xtra.v
Merge remote-tracking branch 'origin' into xc7srl
2019-04-20 10:41:43 -07:00
drams_map.v
…
drams.txt
Added memory_bram "make_outreg" feature
2015-04-09 16:08:54 +02:00
ff_map.v
Tidy up, fix for -nosrl
2019-04-21 15:33:03 -07:00
lut_map.v
Changes required for VPR place and route synth_xilinx.
2019-03-01 12:02:27 -08:00
Makefile.inc
Cleanup, call pmux2shiftx even without -nosrl
2019-04-22 12:14:37 -07:00
synth_xilinx.cc
Add -nocarry option to synth_xilinx
2019-04-24 16:46:41 -07:00
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