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18 lines
473 B
Plaintext
18 lines
473 B
Plaintext
# Port mismatch — gate is missing an input port from gold.
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# The pass should error because ports don't match.
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design -reset
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read_verilog <<EOF
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module gold(input clk, input [7:0] a, b, output reg [7:0] q);
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always @(posedge clk)
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q <= a + b;
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endmodule
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module gate(input clk, input [7:0] a, output reg [7:0] q);
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always @(posedge clk)
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q <= a;
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endmodule
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EOF
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proc; opt_clean
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logger -expect error "Input port.*has no match" 1
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cone_partition -v gold gate
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