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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-08 20:47:34 +02:00
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f845bf3e832676d240ee62fae7819aa6df5296cc
yosys/frontends
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Mike InouyeandChris Pearce 0314db80ea Correctly reset Verific flags to Yosys defaults after -import and warn this has occurred.
Co-authored-by: Chris Pearce <[email protected]>
Signed-off-by: Mike Inouye <[email protected]>
2025-07-25 19:15:01 +00:00
..
aiger
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
aiger2
aiger2: Clean debug print
2024-12-10 14:27:55 +01:00
ast
Merge pull request #4959 from YosysHQ/krys/primitive_array_error
2025-07-21 10:26:00 +12:00
blif
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
json
…
liberty
Liberty file caching with new libcache command
2025-04-03 13:39:35 +02:00
rpc
…
rtlil
read_rtlil: warn on assigns after switches in case rules
2024-11-21 22:41:13 +01:00
verific
Correctly reset Verific flags to Yosys defaults after -import and warn this has occurred.
2025-07-25 19:15:01 +00:00
verilog
verilog: add support for SystemVerilog string literals.
2025-07-03 20:51:12 -06:00
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