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f80fe8dc22ca2b3639b7b0bbff69458addb05432
yosys
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tests
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arch
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Alberto Gonzalez
f80fe8dc22
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 02:41:08 +00:00
..
anlogic
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
common
Merge pull request
#1574
from YosysHQ/eddie/xilinx_lutram
2019-12-16 21:48:21 -08:00
ecp5
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
efinix
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
2020-02-05 10:47:31 -08:00
gowin
Add opt_lut_ins pass. (
#1673
)
2020-02-03 14:57:17 +01:00
ice40
Change attribute search value to specify precise location instead of simple line number.
2020-02-24 02:41:08 +00:00
xilinx
xilinx: Add support for LUT RAM on LUT4-based devices.
2020-02-07 09:03:22 +01:00
run-test.sh
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
