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yosys/tests/verific
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Roland CoeurjolyandN. Engelhardt bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <[email protected]>
Co-authored-by: Roland Coeurjoly <[email protected]>
2024-09-10 12:52:42 +02:00
..
.gitignore
Add test example
2023-02-27 09:24:04 +01:00
bounds.vhd
Add left and right bound properties to wire. Add test. Fix printing
2024-09-10 12:52:42 +02:00
bounds.ys
Add left and right bound properties to wire. Add test. Fix printing
2024-09-10 12:52:42 +02:00
case.sv
Add test example
2023-02-27 09:24:04 +01:00
case.ys
Add test example
2023-02-27 09:24:04 +01:00
clocking.ys
Fix verific clocking when no driver exist
2024-01-18 08:47:04 +01:00
enum_values.sv
verific: Fix enum_values support and signed attribute values
2023-03-15 09:51:36 +01:00
enum_values.ys
verific: Fix enum_values support and signed attribute values
2023-03-15 09:51:36 +01:00
memory_semantics.ys
Add -nordff to test
2024-02-06 10:36:30 +01:00
range_case.sv
Added ranged case check
2023-02-27 09:24:04 +01:00
range_case.ys
Added ranged case check
2023-02-27 09:24:04 +01:00
rom_case.ys
verific: import attributes on ports
2023-10-20 18:31:41 +02:00
run-test.sh
Add test example
2023-02-27 09:24:04 +01:00