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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-08 12:44:23 +02:00
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f73c6a9c9ac1dcaee9ce283c73a6cf9fae07bc6e
yosys/frontends
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Emil J. Tywoniak e5171d6aa1 verific: support single_bit_vector
2025-05-12 13:23:29 +02:00
..
aiger
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
aiger2
aiger2: Clean debug print
2024-12-10 14:27:55 +01:00
ast
rtlil: enable single-bit vector wires
2025-05-12 13:23:29 +02:00
blif
rtlil: represent Const strings as std::string
2024-10-14 06:28:12 +02:00
json
fix handling of escaped chars in json backend and frontend
2022-02-18 17:13:09 +01:00
liberty
Liberty file caching with new libcache command
2025-04-03 13:39:35 +02:00
rpc
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
rtlil
read_rtlil: warn on assigns after switches in case rules
2024-11-21 22:41:13 +01:00
verific
verific: support single_bit_vector
2025-05-12 13:23:29 +02:00
verilog
verilog_parser.y: Delete unused TOK_ID
2025-05-05 10:04:13 +12:00
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