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luke
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yosys
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f71e27dbf15d063ca45378ff2eb2d8102220f199
yosys
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backends
T
History
Clifford Wolf
f71e27dbf1
Remove auto_wire framework (smarter than the verilog standard)
2013-11-24 17:29:11 +01:00
..
autotest
Added modelsim support to autotest
2013-11-24 15:10:43 +01:00
blif
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
edif
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
ilang
Remove auto_wire framework (smarter than the verilog standard)
2013-11-24 17:29:11 +01:00
intersynth
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
spice
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
verilog
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
