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f71c2dcca6b63ad3cbd3d5b6f51f67f9cd85f03e
yosys/tests
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Zachary Snow f71c2dcca6 sv: carry over global typedefs from previous files 
This breaks the ability to use a global typename as a standard
identifier in a subsequent input file. This is otherwise backwards
compatible, including for sources which previously included conflicting
typedefs in each input file.
2021-03-17 15:53:52 -04:00
..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
2021-02-23 17:39:58 +01:00
asicworld
Fix FIRRTL to Verilog process instance subfield assignment.
2019-02-25 16:18:13 -08:00
bram
tests/bram: Do not generate write address collisions.
2021-03-08 16:53:03 +01:00
errors
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
2018-10-25 02:37:56 +03:00
fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
liberty
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
lut
Forgot to commit
2019-07-16 12:44:26 -07:00
memfile
Added 'set -e' into tests/memfile/run-test.sh
2020-02-06 10:45:40 -03:00
memories
tests: Parallelize
2020-09-21 15:07:02 +02:00
opt
opt_clean: Remove init attribute bits together with removed DFFs.
2021-03-15 17:16:53 +01:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_arst: Add special-casing of clock signal in conditionals.
2021-03-15 17:17:29 +01:00
realmath
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
assertpmux: Fix crash on unused $pmux output.
2021-02-22 23:30:28 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
simple
verilog: fix buf/not primitives with multiple outputs
2021-03-17 11:44:03 -04:00
simple_abc9
Set aside extraneous tests in simple_abc9 test suite
2021-03-01 12:13:11 -05:00
smv
Progress in SMV back-end
2015-06-19 14:08:46 +02:00
sva
Fix "verific -extnets" for more complex situations
2019-03-26 14:17:46 +01:00
svinterfaces
Fix typo in tests/svinterfaces/runone.sh
2019-05-03 14:40:51 +02:00
svtypes
Add typedef input/output test
2021-01-18 17:31:22 +01:00
techmap
Add tests for some common techmap files.
2021-02-24 01:07:34 +01:00
tools
memory_dff: Remove now-useless write port handling.
2021-03-08 20:16:29 +01:00
unit
Build hotfix in tests/unit/Makefile
2016-12-11 10:58:49 +01:00
various
blackbox: Include whiteboxed modules
2021-03-17 13:58:04 +00:00
verilog
sv: carry over global typedefs from previous files
2021-03-17 15:53:52 -04:00
vloghtb
bugfix in blif front-end
2015-05-18 11:15:49 +02:00
gen-tests-makefile.sh
tests: Parallelize
2020-09-21 15:07:02 +02:00