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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 18:01:44 +02:00
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f65fc845e53e12d01077604aa077c93fa3cac7f2
yosys/techlibs
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Eddie Hung f65fc845e5 xilinx: improve specify for DSP48E1
2020-03-04 11:31:12 -08:00
..
achronix
Remove executable flag from files
2020-02-15 10:36:44 +01:00
anlogic
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
common
Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
2020-02-27 10:17:29 -08:00
coolrunner2
coolrunner2: Attempt to give wires/cells more meaningful names
2020-03-02 01:40:57 -08:00
easic
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
ecp5
synth_ecp5: use +/abc9_model.v
2020-02-27 10:17:29 -08:00
efinix
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
gowin
Removing cells_sim.v from bram techmap pass
2020-02-06 14:38:29 -06:00
greenpak4
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
ice40
ice40: add delays to SB_CARRY
2020-02-27 10:17:29 -08:00
intel
Add log_experimental() and experimental() API and "yosys -x"
2020-01-27 18:27:47 +01:00
sf2
synth_*: call 'opt -fast' after 'techmap'
2020-02-05 18:39:01 -08:00
xilinx
xilinx: improve specify for DSP48E1
2020-03-04 11:31:12 -08:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
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