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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 20:36:44 +02:00
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f657fed24cb930900e31f72c33292b37d1bddf72
yosys/backends
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Alberto Gonzalez f657fed24c Clean up pseudo-private member usage in backends/verilog/verilog_backend.cc.
2020-04-01 05:25:10 +00:00
..
aiger
xaiger: remove some unnecessary operations ...
2020-03-06 10:51:47 -08:00
blif
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
btor
Use cell name for btor bad state props when it is a public name
2019-11-14 11:57:38 +01:00
edif
Clean up pseudo-private member usage in backends/edif/edif.cc.
2020-04-01 04:37:07 +00:00
firrtl
remove include where not used
2020-03-13 14:55:53 +01:00
ilang
Clean up pseudo-private member usage in backends/ilang/ilang_backend.cc.
2020-04-01 03:08:39 +00:00
intersynth
substr() -> compare()
2019-08-07 12:20:08 -07:00
json
json: Change compat mode to directly emit ints <= 32 bits
2020-02-09 01:01:18 -08:00
protobuf
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
simplec
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
2019-08-06 04:47:55 +02:00
smt2
Do not change solver output parsing for non-exists-forall problems.
2020-03-26 23:00:00 +00:00
smv
substr() -> compare()
2019-08-07 12:20:08 -07:00
spice
Clean up pseudo-private member usage in backends/spice/spice.cc.
2020-04-01 04:56:52 +00:00
table
Add "whitebox" attribute, add "read_verilog -wb"
2019-04-18 17:45:47 +02:00
verilog
Clean up pseudo-private member usage in backends/verilog/verilog_backend.cc.
2020-04-01 05:25:10 +00:00
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