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luke
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yosys
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f6579282d73aec055e2fc4ebebd1b6313da248fd
yosys
/
frontends
/
verilog
T
History
Clifford Wolf
02e6f2c5be
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
const2ast.cc
Fixed handling of unsized constants in verilog frontend
2014-01-24 15:05:24 +01:00
lexer.l
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
Makefile.inc
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
parser.y
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
preproc.cc
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
verilog_frontend.cc
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
verilog_frontend.h
Added Verilog support for "`default_nettype none"
2014-02-17 14:28:52 +01:00
