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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-31 18:24:48 +02:00
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f60b77a7f01ebffe57a5d74e2e7a42e0dbf449e3
yosys/techlibs
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History
Miodrag Milanović edb95c69a9 Merge pull request #4084 from jix/scopeinfo
$scopeinfo support
2024-02-12 09:51:22 +01:00
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achronix
techlibs: fix typo in help message
2023-11-13 16:29:52 +13:00
anlogic
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common
Merge pull request #4084 from jix/scopeinfo
2024-02-12 09:51:22 +01:00
coolrunner2
Blackbox all whiteboxes after synthesis
2021-03-17 21:07:20 +00:00
easic
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ecp5
ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 15:28:13 +00:00
efinix
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fabulous
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gatemate
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gowin
gowin: Fix SDP write enable port.
2024-01-30 17:06:59 +10:00
greenpak4
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ice40
opt_lut: Replace -dlogic with -tech ice40
2024-01-15 12:35:21 +01:00
intel
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intel_alm
intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
lattice
lattice: Disable broken port configuration in bram inference
2023-12-21 10:47:40 +01:00
nexus
nexus: Fix format strings to remove space padding
2023-12-03 10:36:34 +01:00
quicklogic
Fix Windows build by forcing initialization order, fixes #4068
2024-01-02 11:26:48 +01:00
sf2
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
xilinx
tests: use /usr/bin/env for bash.
2023-08-12 11:59:39 +10:00
.gitignore
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