yosys/techlibs at f46ef47893b4d2cb01fc5914fe0ee89d206f686f - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 02:57:40 +02:00

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History

Miodrag Milanovic a3c16a0565 Fix TRELLIS_FF simulation model

2019-08-31 11:12:06 +02:00

..

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Fix missing newline at end of file

2019-08-22 18:09:37 +02:00

Missing newline

2019-08-20 20:37:52 -07:00

Fix spacing

2019-08-06 16:47:55 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Fix TRELLIS_FF simulation model

2019-08-31 11:12:06 +02:00

Fix missing newline at end of file

2019-08-22 18:06:36 +02:00

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Rename boxes too

2019-08-29 07:03:32 -07:00

techlibs/intel: Clean up Makefile

2019-08-05 11:22:11 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl

2019-08-30 09:37:32 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00