Clifford Wolf 483c99fe46 Added "design -push" and "design -pop"

2014-02-20 23:28:59 +01:00

..

bitpattern.h

initial import

2013-01-05 11:13:26 +01:00

calc.cc

Added $bu0 cell (for easy correct $eq/$ne mapping)

2013-12-28 12:02:14 +01:00

celltypes.h

Added $slice and $concat to CellTypes list

2014-02-07 19:50:44 +01:00

consteval.h

Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux

2014-01-03 17:30:50 +01:00

driver.cc

Added echo command

2014-02-07 14:17:00 +01:00

log.cc

Added -v<level> option and some minor driver cleanups

2013-11-17 13:26:31 +01:00

log.h

Some improvements in log_dump_val_worker() templates

2014-01-17 23:14:17 +01:00

register.cc

Added echo command

2014-02-07 14:17:00 +01:00

register.h

Added "design -push" and "design -pop"

2014-02-20 23:28:59 +01:00

rtlil.cc

Improved checking of internal cell conventions

2014-02-08 19:13:49 +01:00

rtlil.h

Added generic RTLIL::SigSpec::parse_sel() with support for selection variables

2014-02-06 19:22:46 +01:00

satgen.h

Added $slice and $concat cell types

2014-02-07 17:44:57 +01:00

sigtools.h

Some fixes to improve determinism

2013-08-09 12:42:32 +02:00