Clifford Wolf f3ff29d410 Fixed instantiating multi-bit ports in edif backend

2014-02-21 13:10:36 +01:00

..

autotest

Fixed gentb_constant handling in autotest backend

2013-12-04 09:09:42 +01:00

blif

Renamed "write_blif -subckt" to "write_blif -icells" and added -gates and -param

2014-02-21 10:40:15 +01:00

btor

modified btor synthesis script for correct use of splice command.

2014-02-12 13:38:28 +01:00

edif

Fixed instantiating multi-bit ports in edif backend

2014-02-21 13:10:36 +01:00

ilang

Added support for dump -append

2014-02-04 23:45:30 +01:00

intersynth

beautified write_intersynth

2014-01-25 20:16:38 +01:00

spice

Added "top" attribute to mark top module in hierarchy

2013-11-24 05:03:43 +01:00

verilog

Added $slice and $concat cell types

2014-02-07 17:44:57 +01:00