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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 11:59:46 +02:00
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f362e1db0e9a71ecb3998d092d96d1db9e83ee98
yosys/techlibs/intel
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Miodrag Milanovic 09eef69e31 synth_intel: fix broken dsp mapping
2026-06-22 17:51:26 +02:00
..
common
Fixed data/address width parameters
2024-03-06 02:45:07 +01:00
cyclone10lp
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
cycloneive
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
max10
Removed SystemVerilog module end label
2024-03-19 01:31:36 +01:00
CMakeLists.txt
synth_intel: fix broken dsp mapping
2026-06-22 17:51:26 +02:00
synth_intel.cc
synth_intel: fix broken dsp mapping
2026-06-22 17:51:26 +02:00
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