Clifford Wolf e38b2ac648 Merge pull request #1147 from YosysHQ/clifford/fix1144 ...

Improve specify dummy parser

2019-07-03 12:30:37 +02:00

..

aiger

Replace log_assert() with meaningful log_error()

2019-06-28 12:54:44 -07:00

ast

Add "read_verilog -pwires" feature, closes #1106

2019-06-19 14:38:50 +02:00

blif

Add missing "[options]" to read_blif help

2019-02-08 12:41:39 -08:00

ilang

Make the generated *.tab.hh include all the headers needed to define the union.

2019-05-14 21:07:26 -07:00

json

Add upto and offset to JSON ports

2019-06-21 19:47:25 +02:00

liberty

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

verific

Only support Symbiotic EDA flavored Verific

2019-06-02 10:14:50 +02:00

verilog

Merge pull request #1147 from YosysHQ/clifford/fix1144

2019-07-03 12:30:37 +02:00