Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 03:52:06 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
f2f5ecd83468fc94bf1ec8d72734fa531d0b2b32
yosys/frontends
T
History
Clifford Wolf 7cfae2c52f Use mem2reg on memories that only have constant-index write ports
Signed-off-by: Clifford Wolf <[email protected]>
2019-03-01 13:35:09 -08:00
..
ast
Use mem2reg on memories that only have constant-index write ports
2019-03-01 13:35:09 -08:00
blif
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
ilang
Add "read_ilang -[no]overwrite"
2018-12-23 15:45:09 +01:00
json
Consistent use of 'override' for virtual methods in derived classes.
2018-07-20 23:51:06 -07:00
liberty
Fix typographical and grammatical errors and inconsistencies.
2019-01-02 13:12:17 +00:00
verific
Improve "read" error msg
2019-02-28 20:34:42 -08:00
verilog
Bugfix in Verilog string handling
2019-01-05 12:10:24 +01:00
Powered by Gitea Version: 1.27.2 Page: 1542ms Template: 5ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API