mirror of https://github.com/YosysHQ/yosys.git
155 lines
4.1 KiB
Plaintext
155 lines
4.1 KiB
Plaintext
read_verilog -sv dsp_equiv.sv
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design -save src
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# y = a*b + c (unsigned)
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design -load src
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hierarchy -top mac_add_u
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proc
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design -stash gold
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design -load src
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hierarchy -top mac_add_u
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synth_nexus -family lifcl -noiopad
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select -assert-count 1 t:MULTADDSUB18X18
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read_verilog +/lattice/cells_sim_nexus.v
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hierarchy -top mac_add_u
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flatten
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proc
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design -stash gate
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design -copy-from gold -as gold mac_add_u
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design -copy-from gate -as gate mac_add_u
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miter -equiv -make_assert -flatten gold gate equiv
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sat -seq 1 -set-init-zero -prove-asserts -verify equiv
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# y = a*b + c (signed)
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design -load src
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hierarchy -top mac_add_s
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proc
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design -stash gold
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design -load src
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hierarchy -top mac_add_s
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synth_nexus -family lifcl -noiopad
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select -assert-count 1 t:MULTADDSUB18X18
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read_verilog +/lattice/cells_sim_nexus.v
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hierarchy -top mac_add_s
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flatten
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proc
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design -stash gate
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design -copy-from gold -as gold mac_add_s
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design -copy-from gate -as gate mac_add_s
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miter -equiv -make_assert -flatten gold gate equiv
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sat -seq 1 -set-init-zero -prove-asserts -verify equiv
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# y = c - a*b (unsigned)
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design -load src
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hierarchy -top mac_sub_u
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proc
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design -stash gold
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design -load src
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hierarchy -top mac_sub_u
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synth_nexus -family lifcl -noiopad
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select -assert-count 1 t:MULTADDSUB18X18
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read_verilog +/lattice/cells_sim_nexus.v
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hierarchy -top mac_sub_u
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flatten
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proc
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design -stash gate
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design -copy-from gold -as gold mac_sub_u
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design -copy-from gate -as gate mac_sub_u
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miter -equiv -make_assert -flatten gold gate equiv
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sat -seq 1 -set-init-zero -prove-asserts -verify equiv
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# y = c - a*b (signed)
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design -load src
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hierarchy -top mac_sub_s
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proc
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design -stash gold
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design -load src
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hierarchy -top mac_sub_s
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synth_nexus -family lifcl -noiopad
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select -assert-count 1 t:MULTADDSUB18X18
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read_verilog +/lattice/cells_sim_nexus.v
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hierarchy -top mac_sub_s
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flatten
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proc
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design -stash gate
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design -copy-from gold -as gold mac_sub_s
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design -copy-from gate -as gate mac_sub_s
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miter -equiv -make_assert -flatten gold gate equiv
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sat -seq 1 -set-init-zero -prove-asserts -verify equiv
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# y = c - a*b (signed, wide out)
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design -load src
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hierarchy -top mac_wide_s
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proc
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design -stash gold
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design -load src
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hierarchy -top mac_wide_s
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synth_nexus -family lifcl -noiopad
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select -assert-count 1 t:MULTADDSUB18X18
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read_verilog +/lattice/cells_sim_nexus.v
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hierarchy -top mac_wide_s
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flatten
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proc
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design -stash gate
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design -copy-from gold -as gold mac_wide_s
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design -copy-from gate -as gate mac_wide_s
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miter -equiv -make_assert -flatten gold gate equiv
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sat -seq 1 -set-init-zero -prove-asserts -verify equiv
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# y = a*b - c (product is the minuend, cannot map to C - A*B, must not fuse)
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design -load src
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hierarchy -top mac_subrev_u
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proc
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design -stash gold
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design -load src
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hierarchy -top mac_subrev_u
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synth_nexus -family lifcl -noiopad
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select -assert-count 0 t:MULTADDSUB18X18
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read_verilog +/lattice/cells_sim_nexus.v
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hierarchy -top mac_subrev_u
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flatten
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proc
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design -stash gate
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design -copy-from gold -as gold mac_subrev_u
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design -copy-from gate -as gate mac_subrev_u
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miter -equiv -make_assert -flatten gold gate equiv
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sat -seq 1 -set-init-zero -prove-asserts -verify equiv
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# pipelined mul (unsigned)
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design -load src
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hierarchy -top mul_pipe_u
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proc
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design -stash gold
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design -load src
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hierarchy -top mul_pipe_u
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synth_nexus -family lifcl -noiopad
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
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read_verilog +/lattice/cells_sim_nexus.v
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hierarchy -top mul_pipe_u
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flatten
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proc
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design -stash gate
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design -copy-from gold -as gold mul_pipe_u
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design -copy-from gate -as gate mul_pipe_u
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miter -equiv -make_assert -flatten gold gate equiv
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sat -seq 6 -set-init-zero -prove-asserts -verify equiv
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# pipelined mul (signed)
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design -load src
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hierarchy -top mul_pipe_s
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proc
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design -stash gold
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design -load src
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hierarchy -top mul_pipe_s
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synth_nexus -family lifcl -noiopad
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select -assert-count 1 t:MULT18X18 r:REGINPUTA=REGISTER r:REGINPUTB=REGISTER r:REGOUTPUT=REGISTER
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read_verilog +/lattice/cells_sim_nexus.v
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hierarchy -top mul_pipe_s
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flatten
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proc
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design -stash gate
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design -copy-from gold -as gold mul_pipe_s
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design -copy-from gate -as gate mul_pipe_s
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miter -equiv -make_assert -flatten gold gate equiv
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sat -seq 6 -set-init-zero -prove-asserts -verify equiv
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