mirror of https://github.com/YosysHQ/yosys.git
46 lines
1.2 KiB
Systemverilog
46 lines
1.2 KiB
Systemverilog
// https://github.com/YosysHQ/yosys/issues/5906
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module mac_add_u (input [8:0] a, b, input [17:0] c, output [17:0] y);
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assign y = a*b + c;
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endmodule
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module mac_add_s (input signed [8:0] a, b, input signed [17:0] c, output signed [17:0] y);
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assign y = a*b + c;
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endmodule
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module mac_sub_u (input [8:0] a, b, input [17:0] c, output [17:0] y);
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assign y = c - a*b;
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endmodule
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module mac_sub_s (input signed [8:0] a, b, input signed [17:0] c, output signed [17:0] y);
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assign y = c - a*b;
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endmodule
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module mac_subrev_u (input [8:0] a, b, input [17:0] c, output [17:0] y);
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assign y = a*b - c;
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endmodule
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module mac_wide_s (input signed [8:0] a, b, input signed [17:0] c, output signed [29:0] y);
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assign y = c - a*b;
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endmodule
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// https://github.com/YosysHQ/yosys/issues/5929
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module mul_pipe_u (input clk, input [8:0] a, b, output reg [17:0] y);
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reg [8:0] a_r;
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reg [8:0] b_r;
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always @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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module mul_pipe_s (input clk, input signed [8:0] a, b, output reg signed [17:0] y);
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reg signed [8:0] a_r;
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reg signed [8:0] b_r;
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always @(posedge clk) begin
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a_r <= a;
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b_r <= b;
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y <= a_r * b_r;
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end
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endmodule
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