mirror of https://github.com/YosysHQ/yosys.git
27 lines
367 B
Plaintext
27 lines
367 B
Plaintext
read_verilog <<EOT
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module simple(I1, I2, O);
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input wire I1;
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input wire I2;
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output wire O;
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assign O = I1 | I2;
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endmodule
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EOT
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abc -g all
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design -reset
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read_verilog <<EOT
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module simple(I1, I2, O);
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input wire I1;
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input wire I2;
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output wire O;
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assign O = I1 | I2;
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endmodule
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EOT
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techmap
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abc -g AND
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select -assert-count 0 t:$_OR_
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select -assert-count 1 t:$_AND_
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