yosys/techlibs at f0ff31ceea6101cd59ebc6bdff2f253dbbeb06d8 - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 01:48:17 +02:00

Files

T

History

Sylvain Munaut 4f9183d107 ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC

Signed-off-by: Sylvain Munaut <[email protected]>

2019-05-13 12:51:06 +02:00

..

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Merge remote-tracking branch 'origin/master' into clifford/specify

2019-05-03 15:05:57 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Add handling of init attributes in "opt_expr -undriven"

2019-04-30 14:46:12 +02:00

Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master

2019-04-22 09:09:27 +02:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC

2019-05-13 12:51:06 +02:00

Fix formatting for synth_intel.cc

2019-05-09 08:40:05 -07:00

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

Add "stat -tech xilinx"

2019-05-11 09:24:52 +02:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00