Alberto Gonzalez f0afd65035 Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.

2020-02-23 07:22:26 +00:00

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aiger

Add and use SigSpec::reverse()

2020-01-28 10:37:16 -08:00

ast

Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.

2020-02-23 07:22:26 +00:00

blif

Fix parsing of .cname BLIF statements

2019-10-16 09:06:57 +02:00

ilang

read_ilang: do bounds checking on bit indices

2019-11-27 22:24:39 +01:00

json

Update JSON front-end to process new attr/param encoding

2019-08-01 12:48:22 +02:00

liberty

stoi -> atoi

2019-08-07 11:09:17 -07:00

rpc

Fixes for MSVC build

2019-10-04 16:29:46 +02:00

verific

Merge pull request #1667 from YosysHQ/clifford/verificnand

2020-01-30 19:55:53 +01:00

verilog

Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.

2020-02-23 07:22:26 +00:00