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luke
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yosys
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https://github.com/YosysHQ/yosys.git
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f0a8713fea9fea016e5a83fefd9e00a32f4a88d2
yosys
/
frontends
/
ast
T
History
Clifford Wolf
e9fe57c75e
Only allow posedge/negedge with 1 bit wide signals
2016-08-10 19:32:11 +02:00
..
ast.cc
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
ast.h
Added "read_verilog -dump_rtlil"
2016-07-27 15:40:17 +02:00
dpicall.cc
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
genrtlil.cc
Only allow posedge/negedge with 1 bit wide signals
2016-08-10 19:32:11 +02:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
