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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 04:19:56 +02:00
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f09ea16bd18e8ca34170becd4b9f91c495e8753a
yosys/passes
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Miodrag Milanović 2f4c917dac Merge pull request #4181 from povik/ci-cxxstd-fix
ci: Fix CXXSTD typo
2024-02-08 18:55:47 +01:00
..
cmds
Merge pull request #4174 from YosysHQ/claire/overwrite
2024-02-05 23:49:24 +01:00
equiv
equiv_simple: Fix seed handling in non-short mode
2023-10-03 13:05:42 +02:00
fsm
add option to fsm_detect to ignore self-resetting
2023-01-30 16:12:53 +01:00
hierarchy
hierarchy: Without a known top module, derive all deferred modules
2024-02-06 10:31:40 +01:00
memory
Fix printf formats
2024-01-15 12:07:54 +01:00
opt
Merge pull request #4181 from povik/ci-cxxstd-fix
2024-02-08 18:55:47 +01:00
pmgen
Address SigBit/SigSpec confusion issues under c++20
2024-02-08 17:48:36 +01:00
proc
proc_clean: only consider fully-defined switch operands too.
2023-08-12 02:46:31 +02:00
sat
async2sync, clk2fflogic: Add support for $check and $print cells
2024-02-01 20:10:39 +01:00
techmap
Address SigBit/SigSpec confusion issues under c++20
2024-02-08 17:48:36 +01:00
tests
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
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