This website requires JavaScript.
Explore
Help
Register
Sign In
luke
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
eff7e1f360
yosys
/
tests
/
various
/
hierarchy_recursive.v
4 lines
66 B
Verilog
Raw
Blame
History
module
top
(
input
x
,
output
y
)
;
top
top_i
(
.
x
(
x
)
,
.
y
(
y
)
)
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink