Eddie Hung 237415e78c write_xaiger: inherit port ordering from original module

2019-12-27 16:44:18 -08:00

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aiger

write_xaiger: inherit port ordering from original module

2019-12-27 16:44:18 -08:00

blif

RTLIL::S{0,1} -> State::S{0,1}

2019-08-07 11:12:38 -07:00

btor

Use cell name for btor bad state props when it is a public name

2019-11-14 11:57:38 +01:00

edif

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firrtl

Merge pull request #1258 from YosysHQ/eddie/cleanup

2019-08-10 09:52:14 +02:00

ilang

RTLIL::S{0,1} -> State::S{0,1}

2019-08-07 11:12:38 -07:00

intersynth

substr() -> compare()

2019-08-07 12:20:08 -07:00

json

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protobuf

Add aiger and protobuf backends binary support

2019-09-28 09:51:48 +02:00

simplec

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smt2

Bugfix in smtio vcd handling of $-identifiers

2019-10-23 00:04:34 +02:00

smv

substr() -> compare()

2019-08-07 12:20:08 -07:00

spice

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table

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verilog

write_verilog: add -extmem option, to write split memory init files.

2019-11-18 01:27:21 +00:00