mirror of https://github.com/YosysHQ/yosys.git
54 lines
1.5 KiB
Plaintext
54 lines
1.5 KiB
Plaintext
read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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# equivalence checking is somewhat slow (and missing simulation models)
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT9X9
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# Make sure that DSPs are not inferred with -nodsp option
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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synth_gowin -family gw2a -nodsp
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cd top # Constrain all select calls below inside the top module
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select -assert-none t:MULT9X9
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
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hierarchy -top top
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proc
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT18X18
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT36X36
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# We end up with two 18x18 multipliers
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# 36x36 min width is 22
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:MULT18X18
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