yosys/docs/source/code_examples
Krystine Sherwin b3024289c6
Docs: Force read_verilog to avoid verific header
2024-04-13 11:33:04 +12:00
..
axis
extensions Docs: Force read_verilog to avoid verific header 2024-04-13 11:33:04 +12:00
fifo
intro
macc
macro_commands
opt
scrambler
selections
show
stubnets
synth_flow
techmap
.gitignore
primetest.v