Eddie Hung 0f094fba08 Pad all boxes so that all input/output connections specified

2019-05-21 16:19:23 -07:00

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aiger

Pad all boxes so that all input/output connections specified

2019-05-21 16:19:23 -07:00

blif

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

btor

Change "ne" to "neq" in btor2 output

2019-04-19 21:17:12 +02:00

edif

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

firrtl

Fix all warnings that occurred when compiling with gcc9

2019-05-08 10:27:14 +02:00

ilang

Add "real" keyword to ilang format

2019-05-06 12:00:40 +02:00

intersynth

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

json

Revert "write_json to not write contents (cells/wires) of whiteboxes"

2019-04-18 23:05:59 -07:00

protobuf

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

simplec

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

smt2

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

smv

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

spice

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

table

Add "whitebox" attribute, add "read_verilog -wb"

2019-04-18 17:45:47 +02:00

verilog

Fix handling of partial init attributes in write_verilog, fixes #997

2019-05-07 19:55:36 +02:00