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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 03:13:21 +02:00
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ed7cb0b095e0eaf0ced643f7f828ea2c61b939b5
yosys/techlibs/intel_alm
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Eddie Hung 8fbb55f4ab synth_*: no need to explicitly read +/abc9_model.v
2020-05-14 10:33:56 -07:00
..
common
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
Makefile.inc
intel_alm: direct LUTRAM cell instantiation
2020-05-07 21:03:13 +02:00
synth_intel_alm.cc
synth_*: no need to explicitly read +/abc9_model.v
2020-05-14 10:33:56 -07:00
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