yosys/techlibs at ecc22f7fedfa639482dbc55a05709da85116a60f - yosys - Gitea: Git with a cup of tea

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David Shah beab15b77c Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix

ice40: Map unmapped 'mince' DFFs to gate level

2020-03-21 17:35:27 +00:00

..

Remove executable flag from files

2020-02-15 10:36:44 +01:00

synth_*: call 'opt -fast' after 'techmap'

2020-02-05 18:39:01 -08:00

Fix invalid verilog syntax

2020-03-14 14:33:44 +01:00

coolrunner2: Attempt to give wires/cells more meaningful names

2020-03-02 01:40:57 -08:00

Update doc that "-retime" calls abc with "-dff -D 1"

2019-12-30 13:28:29 -08:00

Merge pull request #1716 from zeldin/ecp5_fix

2020-03-09 11:04:08 +01:00

synth_*: call 'opt -fast' after 'techmap'

2020-02-05 18:39:01 -08:00

Removing cells_sim.v from bram techmap pass

2020-02-06 14:38:29 -06:00

synth_*: call 'opt -fast' after 'techmap'

2020-02-05 18:39:01 -08:00

Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix

2020-03-21 17:35:27 +00:00

Add log_experimental() and experimental() API and "yosys -x"

2020-01-27 18:27:47 +01:00

synth_*: call 'opt -fast' after 'techmap'

2020-02-05 18:39:01 -08:00

xilinx: Mark IOBUFDS.IOB as external pad

2020-03-20 14:37:38 +01:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00