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yosys/techlibs/common
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Claire Wolf 3c7122c378 Do not optimize away FFs in "prep" and Verific fron-end 
Signed-off-by: Claire Wolf <[email protected]>
2020-06-09 15:54:14 +02:00
..
.gitignore
…
abc9_map.v
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
2020-05-14 16:44:35 -07:00
abc9_model.v
abc9_ops/xaiger: further reducing Module::derive() calls by ...
2020-05-14 10:33:57 -07:00
abc9_unmap.v
abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_
2020-05-29 17:17:40 -07:00
adff2dff.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cellhelp.py
Progress on cell help messages
2015-10-17 02:35:19 +02:00
cells.lib
…
cmp2lcu.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cmp2lut.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
dff2ff.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
gate2lut.v
Fix invalid verilog syntax
2020-03-14 14:33:44 +01:00
gen_fine_ffs.py
Fix the truth table for $_SR_* cells.
2020-04-15 17:17:48 +02:00
Makefile.inc
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
2020-05-14 10:33:56 -07:00
mul2dsp.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
pmux2mux.v
…
prep.cc
Do not optimize away FFs in "prep" and Verific fron-end
2020-06-09 15:54:14 +02:00
simcells.v
Fix the truth table for $_SR_* cells.
2020-04-15 17:17:48 +02:00
simlib.v
Add flooring division operator
2020-05-28 22:59:04 +02:00
synth.cc
synth: only techmap cmp2{lut,lcu} if -lut
2020-04-03 14:28:22 -07:00
techmap.v
Add flooring division operator
2020-05-28 22:59:04 +02:00