Clifford Wolf eab536a203 Merge branch 'master' of github.com:cliffordwolf/yosys

2013-11-03 21:13:21 +01:00

..

autotest

Added support for complex set-reset flip-flops in proc_dff

2013-10-24 16:54:05 +02:00

blif

Added placeholder check to dfflibmap and cleaned up some other placeholder checks

2013-10-31 12:27:07 +01:00

edif

Fixed hex string generation bug in edif backend

2013-10-27 08:21:05 +01:00

ilang

Added -selected option to various backends

2013-09-03 19:10:11 +02:00

intersynth

Ignore explicit unconnected ports in intersynth backend

2013-11-03 09:00:51 +01:00

spice

Fixed handling of boolean attributes (backends)

2013-10-24 11:27:30 +02:00

verilog

Fixed handling of boolean attributes (backends)

2013-10-24 11:27:30 +02:00