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luke
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yosys
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ea79e16bab7abf374f371626297e65c81e00a068
yosys
/
techlibs
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common
T
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Tom Verbeure
87637e8359
Fix some trivial typos.
2021-01-03 23:52:59 -08:00
..
.gitignore
…
abc9_map.v
techmap: Add support for [] wildcards in techmap_celltype.
2020-08-02 22:46:48 +02:00
abc9_model.v
…
abc9_unmap.v
…
adff2dff.v
…
cellhelp.py
…
cells.lib
…
cmp2lcu.v
…
cmp2lut.v
…
dff2ff.v
…
gate2lut.v
…
gen_fine_ffs.py
simcells: Fix reset polarity for $_DLATCH_???_ cells.
2020-06-30 15:32:06 +02:00
Makefile.inc
…
mul2dsp.v
…
pmux2mux.v
…
prep.cc
…
simcells.v
simcells: Fix reset polarity for $_DLATCH_???_ cells.
2020-06-30 15:32:06 +02:00
simlib.v
Fix some trivial typos.
2021-01-03 23:52:59 -08:00
synth.cc
Replace opt_rmdff with opt_dff.
2020-08-07 13:21:03 +02:00
techmap.v
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
2020-08-20 12:44:09 +02:00
