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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 04:19:56 +02:00
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ea79e16bab7abf374f371626297e65c81e00a068
yosys/frontends/ast
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David Shah 09311b6581 dpi: Support for chandle type
Signed-off-by: David Shah <[email protected]>
2021-01-23 22:24:31 +00:00
..
ast.cc
Return correct modname when found in cache.
2020-11-26 13:31:22 +01:00
ast.h
verilog: improved support for recursive functions
2020-12-31 18:33:59 -07:00
dpicall.cc
dpi: Support for chandle type
2021-01-23 22:24:31 +00:00
genrtlil.cc
genrtlil: fix mux2rtlil generated wire signedness
2020-12-22 17:49:16 -07:00
Makefile.inc
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
2014-08-21 12:43:51 +02:00
simplify.cc
Fix input/output attributes when resolving typedef of wire
2021-01-18 17:31:22 +01:00
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