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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 03:23:11 +02:00
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ea23bb8aa4a5b66205a536e607fe8a7c983826ec
yosys/backends
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History
Clifford Wolf ea23bb8aa4 Added "write_smv" skeleton
2015-06-15 00:46:27 +02:00
..
blif
Fixed cstr_buf for std::string with small string optimization
2015-06-11 13:39:49 +02:00
btor
Fixed cstr_buf for std::string with small string optimization
2015-06-11 13:39:49 +02:00
edif
Added EDIF backend support for multi-bit cell ports
2015-02-01 15:43:35 +01:00
ilang
Shorter "dump" options
2015-01-31 23:52:36 +01:00
intersynth
namespace Yosys
2014-09-27 16:17:53 +02:00
json
Improvements in cellaigs.cc and "json -aig"
2015-06-11 10:48:16 +02:00
smt2
Removed debug code from write_smt2
2015-06-14 16:22:06 +02:00
smv
Added "write_smv" skeleton
2015-06-15 00:46:27 +02:00
spice
Renamed extend() to extend_xx(), changed most users to extend_u0()
2014-12-24 09:51:17 +01:00
verilog
$mem cell in verilog backend : grouped writes by clock
2015-06-08 17:35:40 -04:00
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