mirror of https://github.com/YosysHQ/yosys.git
c4bd318e76
First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option. |
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| .. | ||
| tests | ||
| .gitignore | ||
| Makefile.inc | ||
| abc9_map.v | ||
| abc9_model.v | ||
| abc9_unmap.v | ||
| abc9_xc7.box | ||
| abc9_xc7.lut | ||
| abc9_xc7_nowide.lut | ||
| arith_map.v | ||
| brams_init.py | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.py | ||
| cells_xtra.v | ||
| lut_map.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| mux_map.v | ||
| synth_xilinx.cc | ||
| xc3s_mult_map.v | ||
| xc3sda_dsp_map.v | ||
| xc4v_dsp_map.v | ||
| xc5v_dsp_map.v | ||
| xc6s_brams.txt | ||
| xc6s_brams_map.v | ||
| xc6s_dsp_map.v | ||
| xc6s_ff_map.v | ||
| xc7_brams_map.v | ||
| xc7_dsp_map.v | ||
| xc7_ff_map.v | ||
| xc7_xcu_brams.txt | ||
| xcu_brams_map.v | ||
| xcu_dsp_map.v | ||
| xcup_urams.txt | ||
| xcup_urams_map.v | ||