Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-08 02:52:53 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
e8a841467f4ddd85acfcfbcda2cd28d43e75341a
yosys/frontends/verilog
T
History
whitequark f41c7ccfff Merge pull request #1879 from jjj11x/jjj11x/package_decl
support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
..
.gitignore
Add "make coverage"
2018-08-27 14:22:21 +02:00
const2ast.cc
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
Makefile.inc
Add one mode dependency
2020-03-19 16:53:40 +01:00
preproc.cc
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
preproc.h
Add support for SystemVerilog-style `define to Verilog frontend
2020-03-27 16:08:26 +00:00
verilog_frontend.cc
Merge pull request #1811 from PeterCrozier/typedef_scope
2020-03-30 13:55:39 +02:00
verilog_frontend.h
Merge pull request #1811 from PeterCrozier/typedef_scope
2020-03-30 13:55:39 +02:00
verilog_lexer.l
Error duplicate declarations of a typedef name in the same scope.
2020-03-24 14:35:21 +00:00
verilog_parser.y
Merge pull request #1879 from jjj11x/jjj11x/package_decl
2020-04-14 12:40:00 +00:00
Powered by Gitea Version: 1.27.2 Page: 91ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API