mirror of https://github.com/YosysHQ/yosys.git
e97e33d00d
Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs. |
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| .. | ||
| bitpattern.h | ||
| calc.cc | ||
| cellaigs.cc | ||
| cellaigs.h | ||
| celledges.cc | ||
| celledges.h | ||
| celltypes.h | ||
| consteval.h | ||
| cost.h | ||
| driver.cc | ||
| hashlib.h | ||
| log.cc | ||
| log.h | ||
| macc.h | ||
| modtools.h | ||
| register.cc | ||
| register.h | ||
| rtlil.cc | ||
| rtlil.h | ||
| satgen.h | ||
| sigtools.h | ||
| utils.h | ||
| yosys.cc | ||
| yosys.h | ||