mirror of https://github.com/YosysHQ/yosys.git
60 lines
1.3 KiB
Plaintext
60 lines
1.3 KiB
Plaintext
read_rtlil <<EOF
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# Generated by Yosys 0.53+98 (git sha1 780b12271, g++ 15.1.1 -fPIC -O3)
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autoidx 30
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attribute \top 1
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attribute \src "top.v:1.1-21.10"
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module \top
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attribute \src "top.v:7.15-7.18"
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wire output 1 \led
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attribute \src "top.v:9.8-9.9"
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wire \w
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attribute \src "top.v:20.16-20.18"
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cell $not $not$top.v:20$1
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \w
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connect \Y \led
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end
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attribute \module_not_derived 1
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attribute \src "top.v:10.10-18.4"
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cell \CC_MX4 \mux
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connect \D0 1'x
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connect \D1 1'x
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connect \D2 1'x
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connect \D3 { }
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connect \S0 1'x
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connect \S1 1'x
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connect \Y \w
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end
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end
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EOF
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read_verilog -lib -specify <<EOF
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(* abc9_box, lib_whitebox *)
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module CC_MX4 (
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input D0, D1, D2, D3,
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input S0, S1,
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output Y
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);
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specify
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(D0 => Y) = 453;
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(D1 => Y) = 449;
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(D2 => Y) = 488;
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(D3 => Y) = 484;
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(S0 => Y) = 422;
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(S1 => Y) = 385;
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endspecify
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assign Y = S1 ? (S0 ? D3 : D2) :
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(S0 ? D1 : D0);
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endmodule
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EOF
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abc_new -script abc_speed_gia_only.script -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib
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