yosys/techlibs at e7ef7fa443c0b7c7ec9e4bbb15893053aed8c3ce - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 11:29:42 +02:00

Files

T

History

Eddie Hung e7ef7fa443 Reverse bits in INIT parameter for Xilinx, since MSB is shifted first

2019-03-14 09:38:42 -07:00

..

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Merge pull request #772 from whitequark/synth_lut

2019-01-02 15:44:57 +01:00

Unify usage of noflatten among architectures

2019-01-04 11:37:25 +01:00

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

ecp5: Demote conflicting FF init values to a warning

2019-03-04 11:26:20 +00:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module

2019-02-26 09:40:46 -08:00

Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes

2019-03-12 20:14:18 +01:00

Reduce amount of trailing whitespace in code base

2019-02-28 14:58:11 -08:00

Add link to SF2 / igloo2 macro library guide

2019-03-07 09:08:26 -08:00

Reverse bits in INIT parameter for Xilinx, since MSB is shifted first

2019-03-14 09:38:42 -07:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00