Eddie Hung e8f4dc739c Cope WIDTH of ff/latch cells is default of zero

2019-02-06 15:51:12 -08:00

..

.gitignore

Added first help messages for cell types

2015-10-14 16:27:42 +02:00

adff2dff.v

Added adff2dff.v (for techmap -share_map)

2014-08-07 16:14:38 +02:00

cellhelp.py

Progress on cell help messages

2015-10-17 02:35:19 +02:00

cells.lib

Added cells.lib

2015-01-16 15:50:42 +01:00

cmp2lut.v

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

dff2ff.v

Add dff2ff.v techmap file

2017-05-31 11:45:58 +02:00

gate2lut.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

Makefile.inc

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

pmux2mux.v

Added techlibs/common/pmux2mux.v

2014-01-17 20:06:15 +01:00

prep.cc

Fix typographical and grammatical errors and inconsistencies.

2019-01-02 13:12:17 +00:00

simcells.v

Add INIT parameter to all ff/latch cells

2019-02-06 14:16:26 -08:00

simlib.v

Cope WIDTH of ff/latch cells is default of zero

2019-02-06 15:51:12 -08:00

synth.cc

Merge pull request #772 from whitequark/synth_lut

2019-01-02 15:44:57 +01:00

techmap.v

Added $ff and $_FF_ cell types

2016-10-12 01:18:39 +02:00